UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 328

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
326
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAUS
stop
Sets the TAU0EN bit of the PER2 register to 1.
Sets the TPS0 register.
Sets the TMRn register (determines operation mode of
channel).
Sets number of counts to the TDRn register.
Clears the TOEn bit of the TOE0 register to 0.
Sets the TSn bit to 1.
Set value of the TDRn register can be changed.
The TCRn register can always be read.
The TSRn register is not used.
Set values of TMRn register, TOMn, TOLn, TOn, and
TOEn bits cannot be changed.
The TTn bit is set to 1.
The TAU0EN bit of the PER2 register is cleared to 0.
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
The TSn bit automatically returns to 0 because it is a
trigger bit.
The TTn bit automatically returns to 0 because it is a
trigger bit.
Figure 6-43. Operation Procedure When External Event Counter Function Is Used
Software Operation
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEn = 1, and count operation starts.
Counter (TCRn) counts down each time input edge of the
TIn pin has been detected. When count value reaches
0000H, the value of TDRn is loaded to TCRn again, and
the count operation is continued. By detecting TCRn =
0000H, the INTTMn output is generated.
After that, the above operation is repeated.
TEn = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDRn is loaded to TCRn and detection of the
TIn pin input edge is awaited.
TCRn holds count value and stops.
All circuits are initialized and SFR of each channel is
also initialized.
Hardware Status