UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 446
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UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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ATS3 bits of the OPMR register.
444
Cautions 1. TDRn of the master channel must be rewritten during an up status period of slave channel m
TDRm of the slave channel becomes valid from the next carrier period (up and down trigger detection).
Also, the timing of generating the A/D conversion trigger signal can be specified as follows by setting the ATS0 to
For details, refer to 7.3 (19) TAU option mode register (OPMR).
Remarks 1.
• The match interrupts during a up status period of the master channel.
• The match interrupts during a down status period of the master channel.
• The match interrupts during an up and a down status period of the master channel.
• The match interrupt and valley interrupt during an up and a down status period of the master channel .
2. TSn or TSm cannot be set to “1” (forcible restart) while TEn = 1 or TEm = 1. If TSn or TSm is
2.
(The count status is judged by CSF (TSRm register) of the slave channel or the TOn output
level of the master channel). When the value of TDRn is rewritten during a down status
period, the periods of the down status and up status differ and an expected waveform cannot
be output, because the value of TDRn of the rewritten master channel becomes valid at the
next period.
set to “1” while TEn = 1 or TEm = 1, the counter value (TCRn or TCRm) will be illegal and TOn
or TOm will not be able to output the expected waveform.
OPM = 0: n = 00, m = 08, 09
OPM = 1: n = 00, 04, m = 01, 05
OPM: Bit 15 of TAU option mode register (OPMR)
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
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