UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 291

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UPD78F1203MC-CAB-AX

Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1203MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
Note These operation modes are used with the inverter control function. For the inverter control function,
• One-count mode
• Capture & one-count mode
• Up and down count mode
refer to CHAPTER 7 INVERTER CONTROL FUNCTIONS.
Timer operation mode
Table 6-6. Operations from Count Operation Enabled State to TCRn Count Start (2/2)
Note
CHAPTER 6 TIMER ARRAY UNIT TAUS
The waiting-for-start-trigger state is entered by writing 1 to the TSn bit while the
timer is stopped (TEn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDRn to TCRn and the subsequent count
clock performs count down operation (see 6.3 (6) (d) Start timing in one-count
mode).
The waiting-for-start-trigger state is entered by writing 1 to the TSn bit while the
timer is stopped (TEn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRn and the subsequent count clock
performs count up operation (see 6.3 (6) (e) Start timing in capture & one-
count mode).
No operation is carried out from start trigger detection (TSn = 1) until count clock
generation.
The first count clock loads the value of TDRn to TCRn and the subsequent count
clock performs count down operation (see 6.3 (6) (a) Start timing in interval
timer mode and up and down count mode).
User’s Manual U19678EJ1V1UD
Operation when TSn = 1 is set
289

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