UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 348

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8.2 Operation as PWM function
register 0 (TS0) is set to 1, an interrupt (INTTMn) is output, the value set to timer data register n (TDRn) is loaded to
timer counter register n (TCRn), and the counter counts down in synchronization with the count clock. When the
counter reaches 0000H, INTTMn is output, the value of the TDRn register is loaded again to the TCRn register, and
the counter counts down. This operation is repeated until the channel stop trigger bit (TTn) of timer channel stop
register 0 (TT0) is set to 1.
the PWM output (TOm) cycle.
TCRm register loads the value of the TDRm register and the counter counts down to 0000H. When the counter
reaches 0000H, it outputs INTTMm and waits until the next start trigger (INTTMn from the master channel) is
generated.
the PWM output (TOm) duty.
inactive level when the TCRm register of the slave channel becomes 0000H.
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Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
The master channel operates in interval timer mode. If the channel start trigger bit (TSn) of timer channel start
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is
The slave channel operates in one-count mode. By using INTTMn from the master channel as a start trigger, the
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is
PWM output (TOm) goes to the active level one clock after the master channel generates INTTMn and goes to the
Caution To rewrite both TDRn of the master channel and TDRm of the slave channel, a write access is
Remark
Remark
Pulse period = {Set value of TDRn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRm (slave)}/{Set value of TDRn (master) + 1} × 100
0% output:
100% output: Set value of TDRm (slave) ≥ {Set value of TDRn (master) + 1}
necessary two times. The timing at which the values of TDRn and TDRm are loaded to TCRn and
TCRm is upon occurrence of INTTMn of the master channel. Thus, when rewriting is performed
split before and after occurrence of INTTMn of the master channel, the TOm pin cannot output
the expected waveform. To rewrite both TDRn of the master and TDRm of the slave, therefore, be
sure to rewrite both the registers immediately after INTTMn is generated from the master
channel.
n = 00, 02, 04, 06, 08, 10 (78K0R/IB3: n = 02, 04, 06 and 10)
m = n + 1
The duty factor exceeds 100% if the set value of TDRm (slave) > (set value of TDRn (master) + 1), it
summarizes to 100% output.
Set value of TDRm (slave) = 0000H
CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD