UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 910
UPD78F1203MC-CAB-AX
Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1203MC-CAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
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Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
(2) STOP mode release
908
(a) Release by unmasked interrupt request
Standby release signal
When an unmasked interrupt request is generated, the STOP mode is released.
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
4. The STOP instruction cannot be executed when the CPU operates on the 40 MHz internal high-
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and
then execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
speed oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-
speed oscillation clock operation.
(X1 oscillation)
Status of CPU
system clock
High-speed
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
Figure 18-5. STOP Mode Release by Interrupt Request Generation (1/2)
Normal operation
system clock)
Oscillates
(high-speed
instruction
CHAPTER 18 STANDBY FUNCTION
STOP
User’s Manual U19678EJ1V1UD
Oscillation stopped
STOP mode
Interrupt
request
Oscillation stabilization time (set by OSTS)
Oscillation stabilization wait
(HALT mode status)
(set by OSTS)
Oscillates
Wait
Normal operation
system clock)
(high-speed
After the oscillation
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