UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 881

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
Notes 1. CSIIF01 and CSIIF00 bits are not provided in the 78K0R/IB3 and the 38-pin products of the 78K0R/IC3.
Cautions 1. Be sure to clear the following bits to 0.
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction.
When MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0,
MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
Address: FFFD1H
Symbol
Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2)
IF2H
2. IICAIF bit is not provided in the 78K0R/IB3 and the 38-pin and 44-pin products of the 78K0R/IC3. In
3. Those bits are not provided in the 78K0R/IB3. In the case of 78K0R/IB3, be sure to set bits 1 and 2 of
these products, be sure to set bit 3 of the IF1L register to 0.
the IF1H register, and bits 3 and 4 of the IF2L register to 0.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
increases by 2 clocks.
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is
cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit
memory manipulation instruction in C language.
mov a, IF0L
and a, #0FEH
mov IF0L, a
78K0R/IB3
38-pin and 44-pin products of 78K0R/IC3 : Bit 3 of IF1L, Bit 3 of IF1H, and Bits 3 to 7 of
48-pin products of 78K0R/IC3, 78K0R/ID3,
78K0R/IE3
If a program is described in C language using an 8-bit memory manipulation instruction
In this case, even if the request flag of another bit of the same interrupt request flag
XXIFX
7
0
0
1
After reset: 00H
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
6
0
CHAPTER 17 INTERRUPT FUNCTIONS
R/W
User’s Manual U19678EJ1V1UD
5
0
4
0
Interrupt request flag
: Bit 3 of IF1L, Bits 1 to 3 of IF1H, Bits 3 and 4 of
: Bit 3 of IF1H and Bits 3 to 7 of IF2H
IF2L, and Bits 3 to 7 of IF2H
IF2H
3
0
TMIF11
<2>
TMIF10
<1>
TMIF09
<0>
879