UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 618

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

616
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03)
(3) Serial mode register 0n (SMR0n)
SMR0n
Symbol
SMR0n register is a register that sets an operation mode of channel n. It is also used to select an operation
clock (f
(CSI, UART, or I
only in the UART mode.
Rewriting SMR0n register is prohibited when the register is in operation (when SE0n = 1). However, the
MD0n0 bit can be rewritten during operation.
SMR0n register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets SMR0n register to 0020H.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark
Operation clock (f
higher 7 bits of the SDR0n register, a transfer clock (f
Transfer clock f
error controller. When CCS0n = 0, the division ratio of operation clock (f
SDR0n register.
Transfer is started when the above source is satisfied after 1 is set to the SS0 register.
CKS
CCS
STS
CKS
MCK
0n
0n
0n
15
0n
0
1
0
1
0
1
), specify whether the serial clock (f
n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10), q: UART number (q = 0, 1)
Prescaler output clock CK00 set by SPS0 register
Prescaler output clock CK01 set by SPS0 register
Divided operation clock f
Clock input f
Only software trigger is valid (selected for CSI, UART transmission, and simplified I
Valid edge of R
CCS
14
0n
2
C), and an interrupt source. This register is also used to invert the level of the receive data
Figure 13-6. Format of Serial Mode Register 0n (SMR0n) (1/2)
TCLK
13
0
MCK
SCK
is used for the shift register, communication controller, output controller, interrupt controller, and
) is used by the edge detector. In addition, depending on the setting of the CCS0n bit and the
X
from SCKp pin (slave transfer in CSI mode)
12
Dq pin (selected for UART reception)
0
CHAPTER 13 SERIAL ARRAY UNIT
11
0
MCK
specified by CKS0n bit
User’s Manual U19678EJ1V1UD
10
Selection of operation clock (f
0
Selection of transfer clock (f
SCK
Selection of start trigger source
9
0
) may be input or not, set a start trigger, an operation mode
STS
0n
TCLK
8
After reset: 0020H
) is generated.
7
0
TCLK
SIS
0n0
MCK
6
) of channel n
) of channel n
MCK
) is set by the higher 7 bits of the
5
1
R/W
4
0
2
3
0
C).
0n2
MD
2
0n1
MD
1
0n0
MD
0