UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 17

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 15 MULTIPLIER/DIVIDER................................................................................................... 837
CHAPTER 16 DMA CONTROLLER..................................................................................................... 846
14.5 I
14.6 Timing Charts ........................................................................................................................... 830
15.1 Functions of Multiplier/Divider .............................................................................................. 837
15.2 Configuration of Multiplier/Divider........................................................................................ 837
15.3 Register Controlling Multiplier/Divider ................................................................................. 842
15.4 Operations of Multiplier/Divider ............................................................................................ 843
16.1 Functions of DMA Controller .................................................................................................. 846
16.2 Configuration of DMA Controller............................................................................................ 847
16.3 Registers to Controlling DMA Controller............................................................................... 850
16.4 Operation of DMA Controller .................................................................................................. 853
16.5 Example of Setting of DMA Controller................................................................................... 855
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14.5.1 Start conditions .............................................................................................................................782
14.5.2 Addresses .....................................................................................................................................783
14.5.3 Transfer direction specification .....................................................................................................783
14.5.4 Acknowledge (ACK) ......................................................................................................................784
14.5.5 Stop condition ...............................................................................................................................785
14.5.6 Wait...............................................................................................................................................786
14.5.7 Canceling wait...............................................................................................................................788
14.5.8 Interrupt request (INTIICA) generation timing and wait control .....................................................789
14.5.9 Address match detection method..................................................................................................790
14.5.10 Error detection ............................................................................................................................790
14.5.11 Extension code ...........................................................................................................................790
14.5.12 Arbitration....................................................................................................................................791
14.5.13 Wakeup function .........................................................................................................................793
14.5.14 Communication reservation ........................................................................................................796
14.5.15 Cautions......................................................................................................................................800
14.5.16 Communication operations .........................................................................................................801
14.5.17 Timing of I
15.4.1 Multiplication operation.................................................................................................................843
15.4.2 Division operation .........................................................................................................................844
16.4.1 Operation procedure .....................................................................................................................853
16.4.2 Transfer mode...............................................................................................................................854
16.4.3 Termination of DMA transfer .........................................................................................................854
16.5.1 CSI consecutive transmission .......................................................................................................855
16.5.2 Consecutive capturing of A/D conversion results..........................................................................857
C Bus Definitions and Control Methods .............................................................................. 782
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C interrupt request (INTIICA) occurrence ..................................................................809
User’s Manual U19678EJ1V1UD
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