UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 444

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

442
TAUS
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAUS
stop
Remarks 1.
Figure 7-54. Operation Procedure When A/D Conversion Trigger Output Function (Type 1) Is Used
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Sets the TPS0 register.
Sets the TMRn and TMRm registers of two channels to
be used (determines operation mode of channels).
An interval (period) value is set to the TDRn register of
the master channel, and a duty factor is set to the
TDRm register of the slave channel.
Sets the TSn (master) and TSm (slave) bits of the TS0
register to 1 at the same time.
The set values of the TDRn and TDRm registers can be
changed after generation of INTTMn of the master
channel.
The TCRn and TCRm registers can always be read.
The TTn (master) and TTm (slave) bits are set to 1 at
the same time.
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
Determines clock frequencies of CK00 and CK01.
The TSn and TSm bits automatically return to 0
because they are trigger bits.
The TTn and TTm bits automatically return to 0
because they are trigger bits.
2.
OPM = 0: n = 00, m = 08, 09
OPM = 1: n = 00, 04, m = 01, 05
OPM: Bit 15 of TAU option mode register (OPMR)
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
Power-off status
Power-on status. Each channel stops operating.
Channel operating.
(Clock is supplied and some power is consumed.)
TEn = 1, TEm = 1
At the master channel, TCRn loads the value of TDRn and
counts down. When the count value reaches TCRn =
0000H, INTTMn is generated. At the same time, the value of
TDRn is loaded to TCRn, and the counter starts counting
down again.
At the slave channel, the value of the TDRm register is
transferred to TCRm, triggered by the INTTMn signal of the
master channel, and the counter starts counting down.
INTTMm is generated when TCRm = 0000H is detected, and
the count operation is stopped. After that, the above
operation is repeated.
TEn and TEm = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
The master channel starts counting and INTTMn is
generated. Triggered by this interrupt, the slave channel
also starts counting.
TCRn and TCRm hold count values and stop.
All circuits are initialized and SFR of each channel is also
initialized.
Hardware Status