UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 627

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UPD78F1203MC-CAB-AX

Manufacturer Part Number
UPD78F1203MC-CAB-AX
Description
MCU 16BIT 78K0R/LX3 30-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet

Specifications of UPD78F1203MC-CAB-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
RENESAS
Quantity:
15 000
Part Number:
UPD78F1203MC-CAB-AX
Manufacturer:
NEC
Quantity:
20 000
Address: F0124H, F0125H
(9) Serial channel stop register 0 (ST0)
Symbol
ST0
The lower 8 bits of ST0 register can be set with an 1-bit or 8-bit memory manipulation instruction with ST0L.
Note Communication stops while holding the value of the control register and shift register, and the status of
Caution Be sure to clear bits 15 to 4 to “0”.
Remarks 1. n: Channel number (n = 0 to 3)
ST0 register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (ST0n), the corresponding bit (SE0n) of serial channel enable status
register 0 (SE0) is cleared to 0 (operation is stopped). Because ST0n bit is a trigger bit, it is cleared
immediately when SE0n = 0.
ST0 register can set written by a 16-bit memory manipulation instruction.
Reset signal generation clears ST0 register to 0000H.
ST0n
the serial clock I/O pin, serial data output pin, and each error flag (FEF0n: framing error flag, PEF0n:
parity error flag, OVF0n: overrun error flag).
15
0
1
0
2. When the ST0 register is read, 0000H is always read.
No trigger operation
Clears SE0n bit to 0 and stops the communication operation
14
0
Figure 13-12. Format of Serial Channel Stop Register 0 (ST0)
After reset: 0000H
13
0
12
0
CHAPTER 13 SERIAL ARRAY UNIT
11
0
User’s Manual U19678EJ1V1UD
R/W
10
0
Operation stop trigger of channel n
9
0
8
0
7
0
Note
6
0
.
5
0
4
0
ST0
3
3
ST0
2
2
ST0
1
1
ST0
625
0
0

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