D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 839
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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19.2.2
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is
disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to
the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the
division ratio. As the frequency of φ changes, the following points must be noted.
• The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the
• All internal modules basically operate on φ. Note, therefore, that time processing involving the
Bit
Initial value :
R/W
guaranteed operation range of clock cycle time tcyc given in the AC timing table in the
Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz
does not arise.
timers, the SCI, etc., will change when the division ratio changes. The wait time when software
standby is cleared will also change in line with a change in the division ratio.
System Clock Control Register (SCKCR)
Normal
Operating Mode
φ output (Initial value)
Fixed high
:
:
PSTOP
R/W
7
0
R/W
—
6
0
Sleep Mode
φ output
Fixed high
R/W
DIV
5
0
Description
—
—
4
0
Software
Standby Mode
Fixed high
Fixed high
Rev.7.00 Feb. 14, 2007 page 805 of 1108
—
—
3
0
Section 19 Power-Down Modes
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
REJ09B0089-0700
SCK1
R/W
1
0
SCK0
R/W
0
0
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