D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 509
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Clear TDRE flag to 0
Start of transmission
set MPBT bit in SSR
All data transmitted?
Break output?
Initialization
TDRE = 1?
TEND = 1?
<End>
Yes
Yes
Yes
Yes
No
No
No
No
Section 12 Serial Communication Interface (SCI)
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Rev.7.00 Feb. 14, 2007 page 475 of 1108
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit-
data-empty interrupt (TXI)
request, and data is written to
TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
REJ09B0089-0700
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