D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 718
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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Section 17 ROM
17.21
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
programmer mode are summarized below.
Use the specified voltages and timing for programming and erasing: Applied voltages in
excess of the rating can permanently damage the device. Use a PROM programmer that supports
the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory
(FZTAT512V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter. Failure to observe these points may result in damage to the device.
power, fix the RES pin low and place
Powering on and off: When applying or disconnecting V
CC
the flash memory in the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
Use the recommended algorithm when programming and erasing flash memory: The
recommended algorithm enables programming and erasing to be carried out without subjecting the
device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in
FLMCR1 or the P2 or E2 bit in FLMCR2, the watchdog timer should be set beforehand as a
precaution against program runaway, etc.
Do not set or clear the SWE1 and SWE2 bit during execution of a program in flash memory:
Wait for at least 100 μs after clearing the SWE1 and SWE2 bit before executing a program or
reading data in flash memory. When the SWE1 and SWE2 bit is set, data in flash memory can be
rewritten, but addresses H'000000 to H'03FFFF in flash memory can only be read in program-
verify or erase-verify mode when SWE1 = 1, and addresses H'040000 to H'07FFFF in flash
memory can only be read in program-verify or erase-verify mode when SWE2 = 1. Access those
address areas only for verify operations (verification during programming/erasing). Also, do not
clear the SWE1 or SWE2 bit during programming, erasing, or verifying.
Similarly, when using the RAM emulation function the SWE1 bit must be cleared before
executing a program or reading data in flash memory.
However, the RAM area overlapping flash memory space can be read and written to regardless of
whether the SWE1 bit is set or cleared.
Rev.7.00 Feb. 14, 2007 page 684 of 1108
REJ09B0089-0700
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