D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 403
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
- Current page: 403 of 1146
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9.5
9.5.1
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
TCLKA
TCLKB
Interrupts
Interrupt Sources and Priorities
Figure 9.33 Phase Counting Mode Application Example
detection
circuit
Edge
TGR0A (speed control period)
TGR0B (pulse width capture)
TGR0D (buffer operation)
(position period capture)
(position control period)
(speed period capture)
TGR1A
TGR1B
TGR0C
TCNT1
TCNT0
Channel 1
Channel 0
Rev.7.00 Feb. 14, 2007 page 369 of 1108
Section 9 16-Bit Timer Pulse Unit (TPU)
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REJ09B0089-0700
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