D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 171

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

5.6.3
The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: For interrupt sources, it is possible to select DTC activation
request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,
for the respective priorities.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE, and the DISEL bit of MRB in the DTC.
Table 5.11 Interrupt Source Selection and Clearing Control
DTCE
0
1
Legend:
X : The relevant interrupt cannot be used.
× : Don't care
DTC
: The relevant interrupt is used. Interrupt source clearing is performed.
: The relevant interrupt is used. The interrupt source is not cleared.
(The CPU should clear the source flag in the interrupt handling routine.)
Operation
Settings
DISEL
×
0
1
DTC
X
Interrupt Source Selection/Clearing Control
Rev.7.00 Feb. 14, 2007 page 137 of 1108
Section 5 Interrupt Controller
CPU
X
REJ09B0089-0700