D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 737

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

(6) Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make
settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which
points to the start address (H'FFBC00) in on-chip RAM.
Bit 7—Transfer Destination Address Setting Error: This bit is set to 1 when there is an error in
the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is
erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range
of H'00 and H'03 after setting the SCO bit in FCCS to 1 and performing download. Before setting
the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'03 as well as clearing this bit
to 0.
Bit 7
TDER
0
1
Bits 6 to 0—Transfer Destination Address (TDA6 to TDA0): These bits specify the download
start address. A value from H'00 to H'03 can be set to specify the download start address in on-
chip RAM in 4-kbyte units.
A value from H'04 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register
is set to 1 to prevent download from being executed.
Bit
Initial value :
R/W
:
:
Description (Return Value after Download)
Setting of TDA6 to TDA0 is normal
Setting of TDER and TDA4 to TDA0 is H'04 to H'FF and download has been aborted
TDER
R/W
7
0
TDA6
R/W
6
0
TDA5
R/W
5
0
TDA4
R/W
4
0
Rev.7.00 Feb. 14, 2007 page 703 of 1108
TDA3
R/W
3
0
TDA2
R/W
2
0
REJ09B0089-0700
TDA1
R/W
Section 17 ROM
1
0
(Initial value)
TDA0
R/W
0
0