D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 762

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 17 ROM
• No interrupts are accepted during download processing. However, interrupt requests are held,
• When hardware standby mode is entered during download processing, the normal download
• Since a stack area of a maximum 128 bytes is used, the area must be saved before setting the
• If flash memory is accessed by the DTC or BREQ during downloading, the operation cannot
[4] FKEY is cleared to H'00 for protection.
[5] The value of the DPFR parameter must be checked and the download result must be
• Check the value of the DPFR parameter (one byte of start address of the download destination
• If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address
• If the value of the DPFR parameter is different from before downloading, check the SS bit (bit
[6] The operating frequency is set to the FPEFEQ parameter for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general register:
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REJ09B0089-0700
so when processing returns to the user procedure program and interrupts are generated. When
the level-detection interrupt requests are to be held, interrupts must be put until the download
is ended.
cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
SCO bit to 1.
be guaranteed. Therefore, access by the DTC or BREQ must not be executed.
confirmed.
A recommended procedure for confirming the download result is shown below.
specified by FTDAR). If the value is H'00, download has been performed normally. If the
value is not H'00, the source that caused download to fail can be investigated by the
description below.
setting of the download destination in FTDAR may be abnormal. In this case, confirm the
setting of the TDER bit (bit 7) in FTDAR.
2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection
and FKEY register setting were normal, respectively.
ER0).
The settable range of the FPEFEQ parameter is 2 MHz to 25 MHz.
When the frequency is set out of this range, an error is returned to the FPFR parameter of the
initialization program and initialization is not performed. For details on the frequency setting,
see the description in 17.23.2 (2) (a) Flash programming/erasing frequency parameter
(FPEFEQ: general register ER0 of CPU).