D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 31
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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17.26 Flash Memory Emulation in RAM ................................................................................... 741
17.27 Switching between User MAT and User Boot MAT ........................................................ 744
17.28 PROM Mode..................................................................................................................... 746
17.29 Further Information........................................................................................................... 754
Section 18 Clock Pulse Generator .....................................................................793
18.1 Overview........................................................................................................................... 793
18.2 Register Descriptions ........................................................................................................ 794
18.3 Oscillator........................................................................................................................... 796
18.4 Duty Adjustment Circuit ................................................................................................... 800
18.5 Medium-Speed Clock Divider .......................................................................................... 800
18.6 Bus Master Clock Selection Circuit .................................................................................. 800
Section 19 Power-Down Modes ........................................................................801
19.1 Overview........................................................................................................................... 801
19.2 Register Descriptions ........................................................................................................ 803
17.25.1 Hardware Protection ............................................................................................ 738
17.25.2 Software Protection.............................................................................................. 739
17.25.3 Error Protection.................................................................................................... 739
17.27.1 Usage Notes ......................................................................................................... 745
17.28.1 Pin Arrangement of the Socket Adapter .............................................................. 747
17.28.2 PROM Mode Operation....................................................................................... 749
17.28.3 Memory-Read Mode............................................................................................ 750
17.28.4 Auto-Program Mode ............................................................................................ 751
17.28.5 Auto-Erase Mode ................................................................................................. 751
17.28.6 Status-Read Mode................................................................................................ 752
17.28.7 Status Polling ....................................................................................................... 752
17.28.8 Time Taken in Transition to PROM Mode .......................................................... 753
17.28.9 Notes on Using PROM Mode .............................................................................. 753
17.29.1 Serial Communication Interface Specification for Boot Mode............................ 754
17.29.2 AC Characteristics and Timing in PROM Mode ................................................. 781
17.29.3 Procedure Program and Storable Area for Programming Data ............................ 787
18.1.1 Block Diagram ..................................................................................................... 793
18.1.2 Register Configuration......................................................................................... 794
18.2.1 System Clock Control Register (SCKCR) ........................................................... 794
18.3.1 Connecting a Crystal Resonator........................................................................... 796
18.3.2 External Clock Input ............................................................................................ 798
19.1.1 Register Configuration......................................................................................... 802
19.2.1 Standby Control Register (SBYCR) .................................................................... 803
19.2.2 System Clock Control Register (SCKCR) ........................................................... 805
Rev.7.00 Feb. 14, 2007 page xxix of xxxii
REJ09B0089-0700
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