D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 372

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 9 16-Bit Timer Pulse Unit (TPU)
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
0
1
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
9.2.9
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Must always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels *
synchronous clearing through counter clearing on another channel *
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
Rev.7.00 Feb. 14, 2007 page 338 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source
Timer Synchro Register (TSYR)
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Description
TCNTn count operation is stopped
TCNTn performs count operation
:
:
—
—
7
0
—
—
6
0
SYNC5
R/W
5
0
SYNC4
R/W
4
0
SYNC3
R/W
3
0
2
are possible.
SYNC2
R/W
2
0
SYNC1
R/W
1
0
(Initial value)
1
, and
n = 5 to 0
SYNC0
R/W
0
0