MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 991

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRA[7:0]
PB[7:0]
PA[7:0]
Reset
Reset
Field
24.0.5.2
Read: Anytime.
Write: Anytime.
Field
24.0.5.3
Read: Anytime.
Write: Anytime.
Field
7–0
7–0
7–0
W
W
R
R
DDRA7
Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
PB7
Port B — Port B pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O
pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state
is read.
Data Direction Port A — This register controls the data direction for port A. DDRA determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
Port B Data Register (PORTB)
Port A Data Direction Register (DDRA)
on PORTA after changing the DDRA register.
DDRA6
PB6
0
0
6
6
Figure 24-5. Port A Data Direction Register (DDRA)
Figure 24-4. Port B Data Register (PORTB)
Table 24-5. PORTB Field Descriptions
Table 24-4. PORTA Field Descriptions
Table 24-6. DDRA Field Descriptions
DDRA5
PB5
5
0
5
0
DDRA4
PB4
0
0
4
4
Description
Description
Description
DDRA3
PB3
3
0
3
0
DDRA2
PB2
0
0
2
2
DDRA1
PB1
1
0
1
0
DDRA0
PB0
0
0
0
0