MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 409

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4
This section provides a complete functional description of the IICV2.
9.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure
9.4.1.1
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
Freescale Semiconductor
9-9.
SDA
SCL
SDA
SCL
Signal
Signal
Start
Start
Functional Description
I-Bus Protocol
START Signal
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
2
2
Calling Address
Calling Address
3
3
4
4
5
5
Figure 9-9. IIC-Bus Transmission Signals
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
7
7
Read/
Write
Read/
Write
LSB
LSB
8
8
Ack
Ack
Bit
9
Bit
9
XX
Repeated
XXX
Signal
Start
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
1
1
D6
2
2
New Calling Address
D5
3
3
Data Byte
D4
4
4
D3
5
5
D2
6
6
D1
7
7
Figure
Read/
Write
LSB
LSB
D0
8
8
Ack
No
Bit
Ack
9
No
9
Bit
9-9, a START
Signal
Stop
Signal
Stop
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