MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 450

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register
only when RXF flag is set (see
Write: For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
10.3.3.1
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
10.3.3.1.1
450
Register
Name
IDR0
IDR1
IDR2
IDR3
Reset:
W
R
Identifier Registers (IDR0–IDR3)
Figure 10-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
W
W
W
W
R
R
R
R
IDR0–IDR3 for Extended Identifier Mapping
ID28
x
7
Figure 10-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping
Bit 7
ID10
ID2
ID27
= Unused, always read ‘x’
6
x
Section 10.3.2.5, “MSCAN Receiver Flag Register
ID9
ID1
6
MC9S12XDP512 Data Sheet, Rev. 2.21
ID26
5
x
ID8
ID0
5
ID25
4
x
RTR
ID7
4
ID24
IDE (=0)
Section 10.3.2.7, “MSCAN Transmitter
3
x
Section 10.3.2.7, “MSCAN Transmitter
(CANTBSEL)”). For receive buffers,
(CANTBSEL)”). Unimplemented for
ID6
3
ID23
x
2
ID5
2
(CANRFLG)”).
Freescale Semiconductor
ID22
ID4
x
1
1
ID21
Bit 0
ID3
x
0