MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 945

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Routed
PIFP[7:0]
Reset
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling
edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the
corresponding bit in the PIFP register. Writing a “0” has no effect.
Field
23.0.5.46 Port H Data Register (PTH)
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the SCI4 as well as the routed SPI1 and SPI2.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value
of the port register, otherwise the buffered pin input state is read.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if
the routed SPI2 module is enabled. Refer to SPI section for details.The routed SPI1 function takes
precedence over the general purpose I/O function if the routed SPI1 is enabled. Refer to SPI section
for details.
The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled
7–0
SCI
SPI
W
R
PTH7
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
SS2
7
0
Writing a logic level “1” clears the associated flag.
PTH6
SCK2
0
6
Figure 23-48. Port H Data Register (PTH)
Table 23-44. PIFP Field Descriptions
MOSI2
PTH5
TXD4
5
0
MISO2
RXD4
PTH4
0
4
Description
PTH3
SS1
3
0
PTH2
SCK1
0
2
MOSI1
PTH1
1
0
MISO1
PTH0
0
0