MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 319

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.2
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
7.3.2.3
Read or write: Anytime
All bits reset to zero.
Freescale Semiconductor
OC7M[7:0]
FOC[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
OC7M7
FOC7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare
Output Compare Mask Action for Channel 7:0
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
0
0
0
7
7
a successful channel 7 output compare, even if the corresponding pin is setup for output compare.
successful channel 7 output compare.
on any channel occurs at the same time as the successful output compare, then the forced output compare
action will take precedence and the interrupt flag will not get set.
from the output compare 7 data register to the timer port.
OC7M6
FOC6
0
0
0
6
6
Figure 7-5. Output Compare 7 Mask Register (OC7M)
Figure 7-4. Timer Compare Force Register (CFORC)
Table 7-3. CFORC Field Descriptions
Table 7-4. OC7M Field Descriptions
OC7M5
MC9S12XDP512 Data Sheet, Rev. 2.21
FOC5
0
0
0
5
5
OC7M4
FOC4
0
0
0
4
4
Description
Description
OC7M3
FOC3
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
0
3
3
OC7M2
FOC2
0
0
0
2
2
OC7M1
FOC1
0
0
0
1
1
OC7M0
FOC0
0
0
0
0
0
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