MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 753

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Freescale Semiconductor
Address: 0x0023
CDCM[1:0]
ABCM[1:0]
Reset
Field
3–2
1–0
W
R
CDCM
ABCM
00
01
10
11
00
01
10
11
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
= Unimplemented or Reserved
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Table
Table
0
0
6
20-14.
20-15.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Figure 20-6. Debug Control Register2 (DBGC2)
Table 20-13. DBGC2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Table 20-14. CDCM Encoding
Table 20-15. ABCM Encoding
0
0
4
Description
Description
Description
Reserved
Reserved
0
3
CDCM
Chapter 20 S12X Debug (S12XDBGV3) Module
0
2
0
1
ABCM
0
0
755