MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 94

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2.9
This register controls the COP (computer operating properly) watchdog.
Read: Anytime
Write:
The COP time-out period is restarted if one these two conditions is true:
94
1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0.
Reset
RSBCK
WCOP
1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes
2. WCOP, CR2, CR1, CR0:
1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with
2. Changing RSBCK bit from “0” to “1”.
Field
7
6
W
R
1
— Anytime in special modes
— Write once in all other modes
WRTMASK = 0.
Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic
restarts and the user must wait until the next window before writing to ARMCOP.
of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
CRG COP Control Register (COPCTL)
7
or
= Unimplemented or Reserved
RSBCK
0
6
Figure 2-12. CRG COP Control Register (COPCTL)
WRTMASK
Table 2-9. COPCTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
0
0
4
Description
0
0
3
CR2
2
Table 2-10
Freescale Semiconductor
CR1
1
shows the duration
CR0
0