MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 834

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.13 ECLK Control Register (ECLKCTL)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
836
Reset values in emulation modes are identical to those of the target mode.
Reset
NECLK
Field
7
NS
NX
SS
ES
ST
EX
W
R
1
Dependent
NECLK
Mode
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
0
1
0
0
1
0
7
= Unimplemented or Reserved
NCLKX2
1
1
1
1
1
1
1
6
Figure 22-15. ECLK Control Register (ECLKCTL)
Table 22-16. ECLKCTL Field Descriptions
0
0
0
0
0
0
0
0
5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
0
0
0
0
4
Description
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
EDIV1
0
0
0
0
0
0
0
1
Freescale Semiconductor
EDIV0
0
0
0
0
0
0
0
0
Single-Chip
Single-Chip
Single-Chip
Expanded
Expanded
Emulation
Emulation
Special
Special
Normal
Normal
Mode
Test