MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 1024

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.61 Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[7:0] as either input or output.
24.0.5.62 Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[15:8] output pin as either full or reduced. If the
port is used as input this bit is ignored.
1026
RDR0AD1[15:8]
DDR1AD1[7:0]
Reset
Reset
Field
Field
W
W
R
7–0
R
7–0
RDR0AD115 RDR0AD114 RDR0AD113 RDR0AD112 RDR0AD111 RDR0AD110 RDR0AD19
DDR1AD17
0
0
7
7
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
Reduced Drive Port AD1 Register 0
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
DDR1AD16
read on PTAD11 register, when changing the DDR1AD1 register.
to be set to logic level “1”.
Figure 24-64. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Figure 24-63. Port AD1 Data Direction Register 1 (DDR1AD1)
0
0
6
6
Table 24-55. DDR1AD1 Field Descriptions
Table 24-56. RDR0AD1 Field Descriptions
DDR1AD15
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDR1AD14
0
0
4
4
Description
Description
DDR1AD13
0
0
3
3
DDR1AD12
0
0
2
2
DDR1AD11
Freescale Semiconductor
0
0
1
1
DDR1AD10
RDR0AD18
0
0
0
0