P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 79

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
Table 75.
P89V660_662_664_3
Product data sheet
Symbol Parameter
f
T
t
t
t
t
t
t
t
t
t
t
t
t
SPI
SPILEAD
SPILAG
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIA
SPIDIS
SPIDV
SPIOH
SPIR
SPIF
Fig 41. I
SPICYC
output)
output)
(input/
(input/
SCL
SDA
SPI operating frequency
SPI cycle time
SPI enable lead time
SPI enable lag time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI access time
SPI disable time
SPI enable to output
data valid time
SPI output data hold
time
SPI rise time
SPI fall time
2
C-bus interface timing
SPI interface timing
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
SPI outputs (SPICLK,
MOSI, MISO)
SPI inputs (SPICLK,
MOSI, MISO, SS)
t
START or repeated START condition
HD;STA
t
fDA
t
LOW
t
rCL
t
rDA
t
HIGH
Conditions
see
see
see
see
see
master or slave; see
Figure
master or slave; see
Figure
see
see
see
see
see
see
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
t
t
fCL
SU;DAT
42, 43, 44,
42, 43, 44,
Rev. 03 — 10 November 2008
42, 43, 44,
44,
44,
42, 43, 44,
42, 43, 44,
44,
44,
42, 43, 44,
42, 43, 44,
42, 43, 44,
42, 43, 44,
45
45
45
45
t
HD;DAT
45
45
45
45
45
45
45
45
45
80C51 with 512 B/1 kB/2 kB RAM, dual I
repeated START condition
4T
2T
2T
Min
250
250
100
100
STOP condition
cy(clk)
cy(clk)
cy(clk)
0
0
0
0
-
-
-
-
-
Variable clock
P89V660/662/664
T
t
suDAT1
cy(clk)
2000
2000
Max
160
111
100
100
80
-
-
-
-
-
-
-
-
t
SU;STA
/ 4
0.3V
t
SU;STO
t
0.7V
suDAT2
CC
CC
t
f
BUF
osc
Min
222
250
250
111
111
100
100
© NXP B.V. 2008. All rights reserved.
0
0
0
-
-
-
-
-
-
= 18 MHz
0.7V
START
condition
0.3V
002aab861
2
2000
2000
Max
160
111
100
100
C-bus, SPI
80
CC
10
-
-
-
-
-
-
-
-
CC
79 of 89
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns