P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 59

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
Table 46.
Table 47.
Table 48.
Bit addressable; Reset value: 00H
Table 49.
Bit
7
6
5 to 3
2 to 1
0
CPS1
0
0
1
1
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
CMOD - PCA counter mode register (address C1H) bit description
CMOD - PCA counter mode register (address C1H) count pulse select
CCON - PCA counter control register (address 0C0H) bit allocation
CCON - PCA counter control register (address 0C0H) bit description
Symbol
CIDL
WDTE
-
CPS1,
CPS0
ECF
Symbol
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
CF
7
CPS0
0
1
0
1
Rev. 03 — 10 November 2008
CR
6
Description
Counter Idle Control: CIDL = 0 programs the PCA Counter to continue
functioning during Idle mode. CIDL = 1 programs it to be gated off
during idle.
WatchDog Timer Enable: WDTE = 0 disables watchdog timer function
on module 4. WDTE = 1 enables it.
Reserved for future use. Should be set to ‘0’ by user programs.
PCA Count Pulse Select (see
PCA Enable Counter Overflow Interrupt: ECF = 1 enables CF bit in
CCON to generate an interrupt. ECF = 0 disables that function.
Description
PCA Counter Overflow Flag. Set by hardware when the counter rolls
over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by
either hardware or software but can only be cleared by software.
PCA Counter Run Control Bit. Set by software to turn the PCA counter
on. Must be cleared by software to turn the PCA counter off.
Reserved for future use. Should be set to ‘0’ by user programs.
PCA Module 4 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 3 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 2 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 1 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 0 Interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
5
-
80C51 with 512 B/1 kB/2 kB RAM, dual I
Select PCA input
0 Internal clock, f
1 Internal clock, f
2 Timer 0 overflow
3 External clock at ECI/P1[2] pin (max rate = f
CCF4
4
osc
osc
CCF3
Table 47
P89V660/662/664
/ 6
/ 6
3
below).
CCF2
2
© NXP B.V. 2008. All rights reserved.
CCF1
1
osc
2
C-bus, SPI
/ 4)
CCF0
59 of 89
0