P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 33

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
Table 22.
P89V660_662_664_3
Product data sheet
Status code
(S1STA)
08H
10H
18H
20H
28H
Master transmitter mode
Status of the
I
A START
condition has
been transmitted.
A repeat START
condition has
been transmitted.
SLA+W has been
transmitted; ACK
has been
received.
SLA+W has been
transmitted;
NOT-ACK has
been received.
Data byte in
S1DAT has been
transmitted; ACK
has been
received.
2
C-bus hardware
Application software response
to/from S1DAT
Load SLA+W
Load SLA+W or
Load SLA+R
Load data byte or 0
no S1DAT action
or
no S1DAT action
or
no S1DAT action
Load data byte or 0
no S1DAT action
or
no S1DAT action
or
no S1DAT action
Load data byte or 0
no S1DAT action
or
no S1DAT action
or
no S1DAT action
Rev. 03 — 10 November 2008
to S1CON
STA
x
x
1
0
1
1
0
1
1
0
1
80C51 with 512 B/1 kB/2 kB RAM, dual I
STO
0
0
0
0
1
1
0
0
1
1
0
0
1
1
SI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P89V660/662/664
AA
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Next action taken by I
hardware
SLA+W will be transmitted;
ACK bit will be received.
As above; SLA+W will be
transmitted; I
to Master Receiver mode.
Data byte will be transmitted;
ACK bit will be received.
Repeated START will be
transmitted.
STOP condition will be
transmitted;
STO flag will be reset.
STOP condition followed by a
START condition will be
transmitted; STO flag will be
reset.
Data byte will be transmitted;
ACK bit will be received.
Repeated START will be
transmitted.
STOP condition will be
transmitted; STO flag will be
reset.
STOP condition followed by a
START condition will be
transmitted; STO flag will be
reset.
Data byte will be transmitted;
ACK bit will be received.
Repeated START will be
transmitted.
STOP condition will be
transmitted; STO flag will be
reset.
STOP condition followed by a
START condition will be
transmitted; STO flag will be
reset.
© NXP B.V. 2008. All rights reserved.
2
C-bus switches
2
C-bus, SPI
2
C-bus
33 of 89