P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 54

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
P89V660_662_664_3
Product data sheet
Fig 23. SPI master-slave interconnection
CLOCK GENERATOR
SPI
pin is the clock output and input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master devices SPI data register. The
written data is then shifted out of the MOSI pin on the master device into the MOSI pin of
the slave device. Following a complete transmission of one byte of data, the SPI clock
generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if
the SPI Interrupt Enable bit (SPIE) and the SPI interrupt enable bit, ES3, are both set.
An external master drives the Slave Select input pin, SS LOW to select the SPI module as
a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the MOSI
pin can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock.
show the four possible combinations of these two bits.
Table 40.
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Table 41.
Bit
7
6
5
4
3
Bit
Symbol
8-BIT SHIFT REGISTER
MSB master LSB
SPCR - SPI control register (address D5H) bit allocation
SPCR - SPI control register (address D5H) bit description
Symbol
SPIE
SPEN
DORD
MSTR
CPOL
SPIE
7
Rev. 03 — 10 November 2008
SPEN
6
Description
If both SPIE and ES3 are set to one, SPI interrupts are enabled.
SPI enable bit. When set enables SPI.
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
Master/slave select. 1 = master mode, 0 = slave mode.
Clock polarity. 1 = SCK is high when idle (active LOW), 0 = SCK is low
when idle (active HIGH).
DORD
SCK
MISO
MOSI
SS
V
5
DD
80C51 with 512 B/1 kB/2 kB RAM, dual I
V
MISO
MOSI
SS
SCK
SS
MSTR
4
CPOL
P89V660/662/664
3
8-BIT SHIFT REGISTER
MSB slave LSB
CPHA
2
Figure 24
© NXP B.V. 2008. All rights reserved.
SPR1
002aaa528
1
and
2
C-bus, SPI
Figure 25
SPR0
54 of 89
0