ATTINY9-MAHR Atmel, ATTINY9-MAHR Datasheet - Page 34

• Manufacturer Part Number: ATTINY9-MAHR
• Description: IC MCU AVR 1K FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY9-MAHR

• Package / Case: 8-UDFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 1KB (1K x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

8.4.2
34
ATtiny4/5/9/10
VLMCSR – V
CC
• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 8-3 on page
Table 8-3.
• Bit 7 – VLMF: VLM Flag
This bit is set by the VLM circuit to indicate that a voltage level condition has been triggered (see
Table
age at V
• Bit 6 – VLMIE: VLM Interrupt Enable
When this bit is set the VLM interrupt is enabled. A VLM interrupt is generated every time the
VLMF flag is set.
• Bits 5:3 – Res: Reserved Bits
These bits are reserved. For ensuring compatibility with future devices, these bits must be writ-
ten to zero, when the register is written.
Level Monitoring Control and Status register
Bit
0x34
Read/Write
Initial Value
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8-4). The bit is cleared when the trigger level selection is set to “Disabled”, or when volt-
CC
WDP2
rises above the selected trigger level.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VLMF
Watchdog Timer Prescale Select
R
7
0
34.
WDP1
VLMIE
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
6
0
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
–
R
0
R
4
–
0
1024K (1048576) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
Oscillator Cycles
Number of WDT
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
R
3
–
0
VLM2
R
2
0
Reserved
VLM1
R/W
1
0
Typical Time-out at
VLM0
R/W
0
0
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
= 5.0V
VLMCSR
8127D–AVR–02/10