ATTINY9-MAHR Atmel, ATTINY9-MAHR Datasheet - Page 17

• Manufacturer Part Number: ATTINY9-MAHR
• Description: IC MCU AVR 1K FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY9-MAHR

• Package / Case: 8-UDFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 1KB (1K x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6. Clock System
6.1
6.1.1
6.1.2
6.1.3
8127D–AVR–02/10
Clock Subsystems
CPU Clock – clk
I/O Clock – clk
NVM clock - clk
I/O
Figure 6-1
clocks need not be active at a given time. In order to reduce power consumption, the clocks to
modules not being used can be halted by using different sleep modes and power reduction reg-
ister bits, as described in
systems is detailed below.
Figure 6-1.
The clock subsystems are detailed in the sections below.
The CPU clock is routed to parts of the system concerned with operation of the AVR Core.
Examples of such modules are the General Purpose Register File, the System Registers and
the SRAM data memory. Halting the CPU clock inhibits the core from performing general opera-
tions and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usu-
ally active simultaneously with the CPU clock.
NVM
CPU
presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the
ANALOG-TO-DIGITAL
Clock Distribution
PRESCALER
CONVERTER
SWITCH
CLOCK
CLOCK
EXTERNAL
CLOCK
SOURCE CLOCK
clk
ADC
“Power Management and Sleep Modes” on page
CLOCK CONTROL UNIT
I/O MODULES
GENERAL
OSCILLATOR
clk
WATCHDOG
RESET
I/O
LOGIC
WATCHDOG
CLOCK
CORE
CPU
clk
RAM
CPU
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
ATtiny4/5/9/10
clk
NVM
NVM
23. The clock
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