ATTINY9-MAHR Atmel, ATTINY9-MAHR Datasheet - Page 18

• Manufacturer Part Number: ATTINY9-MAHR
• Description: IC MCU AVR 1K FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY9-MAHR

• Package / Case: 8-UDFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 1KB (1K x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6.1.4
6.2
6.2.1
6.2.2
18
Clock Sources
ATtiny4/5/9/10
ADC Clock – clk
Calibrated Internal 8 MHz Oscillator
External Clock
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The ADC is available in ATtiny5/10, only.
All synchronous clock signals are derived from the main clock. The device has three alternative
sources for the main clock, as follows:
See
The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage
and temperature dependent, this clock can be very accurately calibrated by the user. See
16-2 on page
This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0]
in CLKMSR to 0b00. Once enabled, the oscillator will operate with no external components. Dur-
ing reset, hardware loads the calibration byte into the OSCCAL register and thereby
automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory cali-
bration in
When this oscillator is used as the main clock, the watchdog oscillator will still be used for the
watchdog timer and reset time-out. For more information on the pre-programmed calibration
value, see section
To use the device with an external clock source, CLKI should be driven as shown in
The external clock is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10.
Figure 6-2.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in reset during such changes in the clock frequency.
ADC
• Calibrated Internal 8 MHz Oscillator (see
• External Clock (see
• Internal 128 kHz Oscillator (see
Table 6-3 on page 21
Table 16-2 on page
119,
External Clock Drive Configuration
“Calibration Section” on page
Figure 17-39 on page 143
page
on how to select and change the active clock source.
EXTERNAL
18)
119.
SIGNAL
CLOCK
page
19)
page
and
111.
Figure 17-40 on page 143
18)
CLKI
GND
for more details.
8127D–AVR–02/10
Figure
Table
6-2.