MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 33

MCU 16KB FLASH SLIC 20TSSOP

MC9S08EL16CTJ

Manufacturer Part Number
MC9S08EL16CTJ
Description
MCU 16KB FLASH SLIC 20TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08EL16CTJ

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08EL
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI, I2C, SLIC
Maximum Clock Frequency
200 KHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08EL32AUTO, DEMO9S08EL32
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1
2
Table 3-1
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Exit from stop3 is done by asserting RESET, or an asynchronous interrupt pin. The asynchronous interrupt
pins are PIA0-PIA3, PIB0 -PIB3, and PIC0-PIC7. Exit from stop3 can also be done by the low-voltage
detection (LVD) reset, the low-voltage warning (LVW) interrupt, the ADC conversion complete interrupt,
the analog comparator (ACMP) interrupt, the real-time counter (RTC) interrupt, the SLIC wake-up
interrupt, or the SCI receiver interrupt.
If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after
fetching the reset vector. Exit by means of an asynchronous interrupt, analog comparator interrupt, or the
real-time interrupt will result in the MCU fetching the appropriate interrupt vector.
3.6.1.1
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
3.6.1.2
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Freescale Semiconductor
STOPE
ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see
Control Register
When in Stop3 mode with BDM enabled, The S
0
1
1
1
1
shows all of the control bits that affect stop mode selection and the mode selected under various
ENBDM
Stop3 Mode
LVD Enabled in Stop Mode
Active BDM Enabled in Stop Mode
1
0
0
0
x
(BDCSCR)”.
1
Both bits must be 1
LVDE
Either bit a 0
Either bit a 0
Chapter 17, “Development
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
x
x
LVDSE
Table 3-1. Stop Mode Selection
PPDC
x
x
0
0
1
IDD
will be near R
Stop modes disabled; illegal opcode reset if STOP instruction executed
Stop3 with BDM enabled
Stop3 with voltage regulator active
Stop3
Stop2
Support.” If ENBDM is set when the CPU executes a
IDD
levels because internal clocks are enabled.
2
Stop Mode
Section 17.4.1.1, “BDC Status and
Chapter 3 Modes of Operation
Table
3-1. The
33

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