MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 124

• Manufacturer Part Number: MC9S08EL16CTJ
• Description: MCU 16KB FLASH SLIC 20TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08EL16CTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Processor Series: S08EL
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, I2C, SLIC
• Maximum Clock Frequency: 200 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08EL32AUTO, DEMO9S08EL32
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal Clock Source (S08ICSV2)
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal
reference clock is enabled.
8.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
8.4.1.3
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 1024
times the reference frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
8.4.1.4
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
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CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
CLKS bits are written to 00
IREFS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is active or LP bit is written to 0
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor