M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 82

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 8.5 CM2 Register
0
C
1
9
8 /
0 .
B
0
0
0
2
G
7
N
1
o r
o
0 -
Oscillation Stop Detection Register
b7
0
. v
NOTES:
u
1
p
0
0
b6
0
1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM20 bit setting does not
3. When a main clock oscillation stop is detected while the CM20 bit is set to "1", the CM21 bit is set to "1".
4. When the CM20 bit is set to "1" and the CM22 bit is set to "1", do not set the CM21 bit to "0".
5. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not
6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop
, 1
0
change when written.
Although the main clock starts oscillating, the CM21 bit is not set to "0". If the main clock is used as a
CPU clock source after the main clock resumes oscillating, set the CM21 bit to "0" by program.
"1", by program.
If the CM22 bit is set to "0" by program while the main clock stops, the CM22 bit cannot be set to "1"
until the next main clock stop is detected.
detection interrupt is generated.
2
b5
0
0
0
b4
0
5
b3
Page 61
b2
b1
b0
f o
(b7 - b4)
Symbol
3
CM20
CM21
CM22
CM23
3
Bit
0
Symbol
CM2
Oscillation Stop Detection
Enable Bit
CPU Clock
Select Bit 2
Oscillation Stop Detection
Flag
Main Clock Monitor
Flag
Reserved Bit
(5)
(6)
Bit Name
(2)
(3, 4)
Address
000D
(1)
16
0: Disables oscillation stop detect function
1: Enables oscillation stop detect function
0: Clock selected by the CM17 bit
1: On-chip oscillator clock
0: Main clock does not stop
1: Detects a main clock stop
0: Main clock oscillates
1: Main clock stops
Set to "0"
After Reset
00
16
Function
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RO