M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 120
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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M
R
R
10.7 INT Interrupt
e
E
3
. v
J
2
Figure 10.10 IFSR Register
0
C
External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge
sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter-
rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.
For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising
and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding
register to "0" (falling edge).
For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set
in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi
pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is
written to "0" by program.
Figure 10.10 shows the IFSR register.
1
9
0 .
8 /
B
0
0
0
______
2
7
G
N
1
o
o r
0 -
External Interrupt Request Source Select Register
. v
b7
NOTE:
u
1
0
p
0
b6
, 1
0
1. Set this bit to "0" to select a level-sensitive triggering.
2
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
b5
0
0
b4
5
Page 99
b3
b2
b1
b0
______
f o
3
Symbol
IFSR7
IFSR6
IFSR0
IFSR2
IFSR4
IFSR5
IFSR1
IFSR3
3
Bit
0
Symbol
IFSR
INT0 Interrupt Polarity
Select Bit
INT1 Interrupt Polarity
Select Bit
INT2 Interrupt Polarity
Select Bit
INT3 Interrupt Polarity
Select Bit
INT4 Interrupt Polarity
select bit
INT5 Interrupt Polarity
Select Bit
UART0, UART3
Interrupt Source
Select Bit
UART1, UART4
Interrupt Source
Select Bit
Bit Name
(1)
(1)
(1)
(1)
(1)
(1)
Address
031F
16
_______
0: One edge
1 : Both edges
0: One edge
1: Both edges
0: One edge
1: Both edges
0: One edge
1: Both edges
0: One edge
1: Both edges
0: One edge
1: Both edges
0: UART3 bus conflict, start condition
1: UART0 bus conflict, start condition
0: UART4 bus conflict, start condition
1: UART1 bus conflict, start condition
detect, stop condition detect
detect, stop condition detect
detect, stop condition detect
detect, stop condition detect
_______
Function
After Reset
00
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
10. Interrupts
_______
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