M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 253

IC M32C/80 MCU ROMLESS 100LQFP

M30800SAGP-BL#U5

Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30800SAGP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Manufacturer
Quantity
Price
Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
NSC
Quantity:
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Company:
Part Number:
M30800SAGP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
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M
R
R
17.2 Functions
e
E
3
. v
J
2
Table 17.9 Trigger Select Function Settings
NOTES:
0
AD0CON0 Register AD0CON2 Register
C
17.2.1 Resolution Select Function
17.2.2 Sample and Hold Function
17.2.3 Trigger Select Function
17.2.4 DMAC Operating Mode
1
TRG = 0
TRG = 1
9
0 .
8 /
1. A/D0 starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated.
2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion.
B
The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to "1" (10-bit
precision), the A/D conversion result is stored into bits 9 to 0 in the AD0j register (j = 0 to 7). When the
BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the AD0j
register.
When the SMP bit in the AD0CON2 register is set to "1" (with the sample and hold function), A/D conver-
sion rate per pin increases to 28 Ø
The sample and hold function is available in all operating modes. Start the A/D conversion after selecting
whether the sample and hold function is to be used or not.
The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register select the trigger to
start the A/D conversion. Table 17.9 lists settings of the trigger select function.
DMAC operating mode is available with all operating modes. When the A/D converter is in multi-port
single sweep mode or multi-port repeat sweep mode 0, the DMAC operating mode must be used. When
the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled), all A/D conversion
results are stored into the AD00 register. DMAC transfers data from the AD00 register to any memory
space every time an A/D conversion is completed in each pin. 8-bit DMA transfer must be selected for 8-
bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 12. DMAC for instructions.
0
0
0
2
(The A/D conversion in process is aborted.)
7
G
N
1
o
o r
0 -
. v
(1)
u
1
p
0
0
, 1
0
Bit and Setting
2
0
0
5
-
TRG0 = 0
TRG0 = 1
Page 232
f o
3
3
0
AD
cycles for 8-bit resolution and 33 Ø
Software trigger
AD0CON0 register is set to "1"
Falling edge of a signal applied to AD
The timer B2 interrupt request of three-phase motor control timer
The A/D0 starts the A/D conversion when the ADST bit in the
External trigger
Hardware trigger
functions (after the ICTB2 counter completes counting)
(2)
(2)
Trigger
__________
AD
TRG
cycles for 10-bit resolution.
17. A/D Converter

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