M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 66

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 7.3 EWCR0 to EWCR3 Registers
0
C
7.2.4 Bus Timing
1
9
8 /
0 .
B
Bus cycle for the internal memory is basically one BCLK cycle. When the PM12 bit in the PM1 register is
set to "1" (wait state), the bus cycles are two BCLK cycles.
Bus cycles for SFRs are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1"
(2 wait states), the bus cycles are three BCLK cycles.
Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the
EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings.
If the EWCRi04 to EWCRi00 bits are set to "00011
Figure 7.3 shows the EWCRi register. Figures 7.4 to 7.8 show bus timing in an external space.
0
0
0
2
G
7
N
1
o r
o
0 -
External Space Wait Control Register i
. v
b7
u
NOTES:
1
p
0
0
b6
, 1
0
1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L".
2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H".
2
b5
0
0
b4
5
b3
Page 45
b2
b1
b0
f o
EWCRi00
EWCRi01
EWCRi02
EWCRi03
EWCRi04
EWCRi06
Symbol
3
3
(b5)
(b7)
Bit
0
Symbol
EWCR0 to EWCR3
Bus Cycle Select Bit
Nothing is assigned.
When read, its content is indeterminate.
Recovery Cycle Addition
Select Bit
Nothing is assigned.
When read, its content is indeterminate.
Bit Name
Address
0048
2
" (1ø+3ø), bus cycles are four BCLK cycles.
16
, 0049
(i=0 to 3)
0 0 0 0 1: 1 + 1
0 0 0 1 0: 1 + 2
0 0 0 1 1: 1 + 3
0 0 1 0 0: 1 + 4
0 0 1 0 1: 1 + 5
0 0 1 1 0: 1 + 6
0 1 0 1 0: 2 + 2
0 1 0 1 1: 2 + 3
0 1 1 0 0: 2 + 4
0 1 1 0 1: 2 + 5
1 0 0 1 1: 3 + 3
1 0 1 0 0: 3 + 4
1 0 1 0 1: 3 + 5
1 0 1 1 0: 3 + 6
Do not set values other than the above
0: Adds no recovery cycle when
1: Adds a recovery cycle when
b4 b3 b2 b1 b0 (1)
16
, 004A
accessing external space i
accessing external space i
(3)
16
, 004B
Function
16
(2)
After Reset
X0X0 0011
2
RW
RW
RW
RW
RW
RW
RW
7. Bus