M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 142

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 13.1 RLVL Register
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
Exit Priority Register
. v
b7
u
NOTES:
1
0
p
0
b6
, 1
0
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1".
4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it
2
Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0"
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0".
when the DMAII bit to "1".
to "0" before setting the interrupt control register.
b5
0
0
b4
5
Page 121
b3
b2
b1
b0
f o
(b7 - b6)
3
Symbol
RLVL0
RLVL1
RLVL2
DMAII
3
FSIT
(b4)
Bit
0
Symbol
RLVL
Stop/Wait Mode Exit
Minimum Interrupt
Priority Level Control
Bit
High-speed Interrupt
Set Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMA II Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(1)
(2)
Bit Name
Address
009F
16
(4)
b2b1b0
0 0 0: Level 0
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
for normal interrupt
for high-speed interrupt
for interrupt
for DMA II transfer
After Reset
XXXX 0000
Function
2
(3)
RW
RW
RW
RW
RW
RW
13. DMACII