M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 198

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

R
R
M
16.1 Clock Synchronous Serial I/O Mode
e
E
3
. v
J
2
Table 16.1 Clock Synchronous Serial I/O Mode Specifications
NOTES:
0
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmit Start Condition
Receive Start Condition
Interrupt Request Generation Timing • While transmitting, the following conditions can be selected:
Error Detect
Selectable Function
C
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1
lists specifications of clock synchronous serial I/O mode. Table 16.2 lists register settings. Tables 16.3 to
16.5 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level
("H") signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain
output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O mode.
1
9
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit setting in the SiRIC register does not
0 .
8 /
B
0
0
0
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held "L".
change to "1" (interrupt requested).
2
7
G
N
1
o
Item
o r
0 -
. v
u
1
0
0
p
, 1
0
2
0
0
5
Page 177
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
Selected from the CTS function, RTS function or CTS/RTS function disabled
To start transmitting, the following requirements must be met
• While receiving
Overrun error
• CLK polarity
• LSB first or MSB first
• Continuous receive mode
• Serial data logic inverse
Transfer data : 8 bits long
To start receiving, the following requirements must be met
This error occurs when the seventh bit of the next received data is read before reading
- Set the TE bit in the UiC1 register to "1" (transmit enabled)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected
- Set the RE bit in the UiC1 register to "1" (receive enabled)
- Set the TE bit to "1" (transmit enabled)
- Set the TI bit to "0" (data in the UiTB register)
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer):
- The UiIRS bit is set to "1" (transmission completed):
the UiRB register
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
f o
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
2(m+1)
when a data transfer from the UARTi transmit register is completed
Selectable from data transmission or reception in either bit 0 or in bit 7
Data can be received simultaneously by reading the UiRB register
This function inverses transmitted/received data logically
output or input timing
Selectable from the rising edge or falling edge of the transfer clock at transferred data
3
f
3
j
0
(3)
f
j
=f
1
, f
_______
8
, f
2
n
(1)
m
:setting value of the UiBRG register, 00
_______
Specification
________
16. Serial I/O (Clock Synchronous Serial I/O)
_______ _______
_______
(2)
:
(2)
:
16
to FF
16