M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 8

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7. Bus_________________________________________ 39
8. Clock Generation Circuit _______________________ 56
9. Protection ___________________________________ 81
10. Interrupts___________________________________ 82
A-2
7.1 Bus Settings ............................................................................................................. 39
7.2 Bus Control ............................................................................................................... 42
8.1 Types of the Clock Generation Circuit ................................................................... 56
8.2 CPU Clock and BCLK .............................................................................................. 70
8.3 Peripheral Function Clock ....................................................................................... 70
8.4 Clock Output Function ............................................................................................ 71
8.5 Power Consumption Control .................................................................................. 72
8.6 System Clock Protect Function .............................................................................. 80
10.1 Types of Interrupts ................................................................................................. 82
7.1.1 Selecting External Address Bus ...................................................................... 40
7.1.2 Selecting External Data Bus ............................................................................ 40
7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 40
7.2.1 Address Bus and Data Bus .............................................................................. 42
7.2.2 Chip-Select Signal ............................................................................................ 42
7.2.3 Read and Write Signals .................................................................................... 44
7.2.4 Bus Timing ........................................................................................................ 45
7.2.5 ALE Signal ......................................................................................................... 53
7.2.6 RDY Signal ......................................................................................................... 53
7.2.8 External Bus Status when Accessing Internal Space ................................... 55
7.2.7 HOLD Signal ...................................................................................................... 55
7.2.9 BCLK Output ..................................................................................................... 55
8.1.1 Main Clock ......................................................................................................... 65
8.1.2 Sub Clock .......................................................................................................... 66
8.1.3 On-Chip Oscillator Clock ................................................................................. 67
8.1.4 PLL Clock .......................................................................................................... 69
8.3.1 f
8.3.2 f
8.3.3 f
8.5.1 Normal Operating Mode ................................................................................... 72
8.5.2 Wait Mode .......................................................................................................... 73
8.5.3 Stop Mode .......................................................................................................... 75
_______
_________
1
AD ....................................................................................................................................................
C32 ...................................................................................................................................................
, f
8
, f
32
and f
2n .........................................................................................................................
70
70
71