M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 278

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
NOTE:
Table 21.4 Clock Settings (Communication Unit 1)
Table 21.5 Register Settings in Clock Synchronous Serial I/O Mode
Table 21.6 Pin Settings in Clock Synchronous Serial I/O Mode (1)
Table 21.7 Pin Settings (2)
0
P
P
P
P
P
P
C
CCS
GiERC
GiMR
GiCR
GiTB
GiRB
i=0, 1
1
9
7
7
7
7
7
8
Input from ISCLK1
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
P
P
0 .
8 /
B
Transfer Clock
3
4
5
6
7
0
Register
o
o
0
0
0
t r
t r
2
7
G
N
1
o
o r
f
0 -
2n (2)
S I
S I
S I
S I
S I
S I
S I
S I
. v
f
u
1
8
T
C
C
R
T
C
C
R
0
p
0
x
x
, 1
L
L
x
L
L
x
0
F
F
D
D
D
D
K
K
K
K
u
u
2
1
0
1
1
1
0
0
0
n
n
0
CCS1, CCS0
CCS3, CSS2
7 to 0
GMD1, GMD0
CKDIR
UFORM
IRS
TI
TXEPT
RI
TE
RE
–
–
O
O
t c
t c
n I
O
n I
n I
O
n I
0
u
u
5
o i
u
u
o i
p
p
p
p
p t
p t
p t
p t
t u
t u
t u
t u
n
n
Page 257
t u
t u
t u
t u
G1MR Register
Bit
CKDIR Bit
P
P
P
P
P
P
P
P
P
P
S
S
S
S
S
S
S
S
S
S
0
0
1
1
1
1
1
1
1
1
1
2
2
_
_
_
_
_
_
_
_
R
R
f o
3
4
4
5
6
7
7
0
e
e
=
=
=
=
=
=
=
=
3
g
g
1
0
1
0
1
0
1
0
Setting not required when using the
communication unit 1 only
Select transfer clock
Set to "0010 0000
Set to "01
Select internal clock or external clock
Select either LSB first or MSB first
Select what cause the transmit interrupt to be generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Write data to be transmitted
Received data and error flag are stored
3
t s i
t s i
0
r e
r e
S
e
t t
Communication Unit 1
n i
P
P
-
P
-
P
-
P
P
P
2
CCS2 Bit
S
S
S
S
S
g
D
D
"
L
L
L
L
L
8
8
1
1
1
1
1
_
1
0
R
-
_
_
_
_
0
R
e
3
4
6
7
=
e
=
=
=
=
g
0
2
g
t s i
0
0
0
0
CCS Register
"
t s i
r e
r e
P
P
P
P
-
-
-
-
S
S
S
S
C
C
C
C
S
_
_
_
CCS3 Bit
R
3
4
6
e
21. Intelligent I/O (Communication Function)
e
=
=
=
t t
Function
g
1
1
0
n i
1
1
-
t s i
g
r e
communication unit 0 only
Select transfer clock
Setting not required when using the
n
=0) or divide-by-2
P
P
-
-
-
-
-
-
S
S
Communication Unit 0
D
D
1
1
_
R
6
e
=
g
0
t s i
r e
n
P
-
P
-
P
-
P
-
D
D
D
D
(
n
7
7
7
7
=1 to 15).
_
_
_
R
4
5
7
e
=
=
=
g
0
0
0
t s i
r e