M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 104

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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10.2 Software Interrupts
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Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter-
rupts.
10.2.1 Undefined Instruction Interrupt
10.2.2 Overflow Interrupt
10.2.3 BRK Interrupt
10.2.4 BRK2 Interrupt
10.2.5 INT Instruction Interrupt
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The undefined instruction interrupt occurs when the UND instruction is executed.
The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic
operation) and the INTO instruction is executed.
Instructions to set the O flag are :
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
The BRK interrupt occurs when the BRK instruction is executed.
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. For development support tools only.
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 8 to 48 are assigned to the vector table
used for the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt rou-
tine when the INT instruction is executed as when a peripheral function interrupt occurs.
When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the
relocatable vector of specified software interrupt numbers. Where the stack is saved varies depending
on a software interrupt number. ISP is selected as the stack for software interrupt numbers 0 to 31
(setting the U flag to "0"). SP, which is set before the INT instruction is executed, is selected as the stack
for software interrupt numbers 32 to 63 (the U flag is not changed).
With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select)
when an interrupt request is acknowledged. With software interrupt numbers 32 to 48, SP to be used
varies depending on whether the interrupt is generated by the peripheral function interrupt request or by
the INT instruction.
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10. Interrupts