M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 64

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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R
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e
E
3
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J
2
Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate Bus)
0
C
1
9
8 /
0 .
B
0
0
0
Chip-Select Signal
2
G
7
Chip-Select Signal
Chip-Select Signal
N
1
o r
o
0 -
Example 3:
. v
Example 1:
Address Bus
u
1
Address Bus
p
When the microcomputer accesses the external
space j specified by another chip-select signal in the
next cycle after having accessed the external space i,
both address bus and chip-select signal change.
0
0
When the microcomputer accesses the space i
specified by the same chip-select signal in the next
cycle after having accessed the external space i,
the address bus changes but the chip-select signal
does not.
Data Bus
, 1
0
i = 0 to 3
j = 0 to 3, excluding i
(See Figure 6.3 for i, j and p, k)
i = 0 to 3
(See Figure 6.3 for i and k)
NOTE:
Data Bus
2
1. The above applies to the address bus and chip-select signal in two consecutive cycles.
0
CSk
0
CSp
CSk
5
By combining these examples, a chip-select signal added by two or more cycles may be output.
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Address
Access
External
Space i
f o
Address
Access
External
Space i
k = 0 to 3
p= 0 to 3, excluding k
k = 0 to 3
3
Data
3
Data
0
Access
External
Space i
Access
External
Space j
Data
Data
Example 4:
Chip-Select Signal
Example 2:
Chip-Select Signal
When the microcomputer accesses SFRs or the
internal RAM area in the next cycle after having
accessed an external space, the chip-select signal
changes but the address bus does not.
When the microcomputer does not access any
space in the next cycle after having accessed an
external space (no pre-fetch of an instruction is
generated), neither address bus nor chip-select
signal changes.
Address Bus
Address Bus
Data Bus
Data Bus
CSk
CSk
k = 0 to 3
k = 0 to 3
Access
External
Space
Access
External
Space
Address
Address
Data
Data
No Access
Access
SFRs,
Internal
RAM Area
7. Bus