M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 325
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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R
R
M
e
E
3
. v
J
Figure 23.7 V
2
0
1
C
9
0 .
B
8 /
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
0
0
0
2
7
[ Read Timing ]
RD
[ Write Timing ]
N
BCLK
ALE
CSi
ADi
/DBi
ADi
BHE
BCLK
ALE
CSi
ADi
/DBi
ADi
BHE
WR,WRL,
WRH
G
NOTE:
1
NOTE:
o
0 -
o r
. v
1. Varies with operation frequency:
2. Varies with operation frequency:
1
u
0
0
t
t
t
t
t
p
d(AD-ALE)
h(ALE-AD)
h(RD-AD)
ac2(RD-DB)
ac2(AD-DB)
, 1
t
(if external bus cycle is a + b , n=a)
t
(if external bus cycle is a + b , n=a)
t
t
t
(if external bus cycle is a + b , m=(b x 2)-1)
0
d(AD-ALE)
h(ALE-AD)
h(WR-AD)
h(WR-CS)
d(DB-WR)
CC1
2
0
18ns.max
t
0
d(BCLK-ALE)
t
18ns.max
d(BCLK-ALE)
=(tcyc/2-10)ns.min, t
5
=V
=(tcyc/2 x n-20)ns.min (if external bus cycle is a + b , n=a)
=(tcyc/2 x n-10)ns.min (if external bus cycle is a + b , n=a)
=(tcyc/2-10)ns.min,
=(tcyc/2-10)ns.min, t
=(tcyc/2 x m-25)ns.min
=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2)-1)
=(tcyc/2 x p-35)ns.max (if external bus cycle is a + b , p={(a+b-1) x 2}+1)
=(tcyc/2 x n - 20)ns.min
=(tcyc/2 x n -10)ns.min
t
d(BCLK-CS)
18ns.max
t
t
t
18ns.max
Page 304
18ns.max
d(BCLK-AD)
CC2
d(BCLK-CS)
d(BCLK-AD)
18ns.max
t
(2 +2 Bus Cycles)
t
(2 +2 Bus Cycles)
d(AD-ALE)
d(AD-ALE)
t
ac2(AD-DB)
=3.3V Timing Diagram (2)
(1)
(2)
f o
(1)
3
h(RD-CS)
Address
3
Address
h(WR-DB)
t
0
h(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
-2ns.min
=(tcyc/2-10)ns.min
t
h(ALE-AD)
=(tcyc/2-20)ns.min
t
h(ALE-AD)
(2)
(1)
t
t
d(BCLK-RD)
d(BCLK-WR)
18ns.max
t
dz(RD-AD)
18ns.max
8ns.max
t
ac2(RD-DB)
tcyc
tcyc
t
d(DB-WR)
tcyc=
Measurement Conditions:
• V
• Input high and low voltage:
• Output high and low voltage:
(1)
t
t
su(DB-BCLK)
h(BCLK-WR)
CC
f
t
Data output
(BCLK)
-3ns.min
h(BCLK-RD)
(2)
0ns.min
V
V
1
10
=V
IH
OH
9
=1.5V, V
Data input
CC
=1.5V, V
t
2
h(WR-CS)
=3.0 to 3.6V
30ns.min
t
0ns.min
h(RD-DB)
t
IL
h(RD-CS)
t
OL
=0.5V
h(WR-DB)
t
t
h(RD-AD)
h(WR-AD)
Vcc
(2)
=1.5V
23. Electrical Characteristics
1
(1)
=Vcc
(2)
t
h(BCLK-AD)
(1)
(2)
t
0ns.min
t
t
h(BCLK-CS)
0ns.min
Address
0ns.min
h(BCLK-CS)
h(BCLK-AD)
0ns.min
Address
2
=3.3V
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