M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 238
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Manufacturer
Quantity
Price
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R
R
M
e
E
3
. v
J
2
Figure 16.29 SIM Interface Operation
0
C
1
9
0 .
8 /
B
0
0
(1) Transmit Timing
0
Transfer Clock
TE bit in the UiC1
register
TI bit in the UiC1
register
Parity Error Signal
returned from
Receiving End
TXEPT bit in the
UiC0 register
IR bit in the SiTIC
register
Transfer Clock
RE bit in the UiC1
register
Transmit Waveform
from the
Transmitting End
RI bit in the UiC1
register
IR bit in the
SiRIC register
TxDi
Signal Line Level
TxDi
Signal Line Level
2
(2) Receive Timing
7
G
N
1
o
NOTES:
o r
0 -
. v
u
1
i=0 to 4
The above applies under the following conditions:
i=0 to 4
The above applies under the following conditions:
1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit.
2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi
3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the
4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15).
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
• The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated
• The PRYE bit in the UiMR register is set to "1" (parity enabled)
• The STPS bit in the UiMR register is set to "0" (1 stop bit)
0
0
p
pin and parity error signal from the receiving end, is generated.
transmitting end and parity error signal from the TxDi pin, is generated.
when transmission completed)
, 1
0
2
0
(2)
(3)
0
5
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Page 217
Start
ST
ST
ST
ST
Start
bit
bit
D
D
D
D
f o
0
0
0
0
D
D
D
3
D
1
1
1
1
3
0
Tc
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
D
D
D
D
Data is written to
the UiTB register
6
6
6
6
D
D
D
D
7
7
7
7
Parity
Parity
P
P
bit
bit
P
P
SP
SP
SP
SP
Stop
Stop
bit
bit
Set to "0" by an interrupt request acknowledgement or by program
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16(m+1) / f
Tc = 16(m+1) / f
f
m: setting value of the UiBRG register
f
m: setting value of the UiBRG register
j
j
: count source frequency of the UiBRG register (f
: count source frequency of the UiBRG register (f
ST
ST
ST
ST
An interrupt routine
detects "H" or "L"
Data is transferred from the UiTB
register to the UARTi transmit
register
(Note 1)
An "L" signal is applied from the SIM
card due to a parity error
D
D
D
D
0
0
0
0
Read the UiRB register
j
j
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
D
TxDi outputs "L" due to
a parity error
D
D
D
3
3
3
16. Serial I/O (Special Function)
3
D
D
D
D
4
4
4
4
An interrupt routine detects
"H" or "L"
D
D
D
D
5
5
5
5
D
D
D
D
6
6
6
6
D
D
D
D
7
7
7
7
P
P
P
P
1
1
, f
SP
SP
, f
8,
8,
SP
SP
f
2n (4)
f
2n (4)
)
)
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