M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 273
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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3
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2
Figure 21.8 G0IRF Register
9 0
C
. 1
8 /
B
0 0
0
0
7 2
G
N
- 1
o
o r
SI/O Special Communication Interrupt Detect Register 0
. v
1 0
b7
NOTES:
u
0
p
0 0
1. The G0IRF register is used in HDLC data processing mode. Do not use it in clock synchronous serial
2. The SRT0R bit in the IIO4IR register is set to "1" if the IRF3 to IRF0 or BSERR bit is set to "1".
b6
, 1
I/O mode.
0 2
b5
5 0
b4
Page 252
b3
0
b2
0 0
b1
b0
f o
(b1 - b0)
Symbol
BSERR
3
IRF0
IRF1
IRF2
IRF3
(b3)
0 3
Bit
Symbol
G0IRF
Reserved Bit
Bit Stuffing Error
Detect Flag
Reserved Bit
Interrupt Source
Determination
Flag 0
Interrupt Source
Determination
Flag 1
Interrupt Source
Determination
Flag 2
Interrupt Source
Determination
Flag 3
Bit Name
Address
00FE
Set to "0"
0: Not detected
1: Detected
Set to "0"
0: The G0DR register (receive data register)
1: The G0DR register matches the G0CMP0
0: The G0DR register (receive data register)
1: The G0DR register matches the G0CMP1
0: The G0DR register (receive data register)
1: The G0DR register matches the G0CMP2
0: The G0DR register (receive data register)
1: The G0DR register matches the G0CMP3
16
does not match the G0CMP0 register
register
does not match the G0CMP1 register
register
does not match the G0CMP2 register
register
does not match the G0CMP3 register
register
21. Intelligent I/O (Communication Function)
Function
After Reset
00
16
(1, 2)
RW
RW
RW
RW
RW
RW
RW
RW
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